UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 789

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.2 Non-Maskable Interrupts
non-maskable interrupt is not subject to priority control and takes precedence over all the other interrupt request
signals.
edge detection”. "No edge detection" is selected by default. Be sure to specify the valid edge.
the WDTM2.WDM21 and WDTM2.WDM20 bits are set to “01”.
is serviced, as follows (the interrupt request signal with the lower priority is ignored).
as follows.
A non-maskable interrupt request signal is acknowledged even when interrupts are disabled (DI) by the CPU. A
This product has the following two non-maskable interrupt request signals.
• NMI pin input (NMI)
• Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2)
The valid edge of the NMI pin can be selected from four types: “rising edge”, “falling edge”, “both edges”, and “no
The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when
If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority
INTWDT2 > NMI
If a new NMI or INTWDT2 request signal is issued while a non-maskable interrupt is being serviced, it is serviced
(1) If new NMI request signal is issued while non-maskable interrupt is being serviced
(2) If new INTWDT2 request signal is issued while non-maskable interrupt is being serviced
The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI
request signal is acknowledged after the non-maskable interrupt currently under execution has been serviced
(after the RETI instruction has been executed).
If the NP bit is set (1) while a non-maskable interrupt is being serviced, the new INTWDT2 request signal is
held pending.
currently under execution has been serviced (after the RETI instruction has been executed).
If the NP bit is cleared (0) while a non-maskable interrupt is being serviced, the newly generated INTWDT2
request signal is acknowledged (the current non-maskable interrupt servicing is stopped).
Caution For details about the non-maskable interrupt servicing requested by the INTWDT2 signal, see
Figure 21-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2)
21.2.2 (2) From INTWDT2 signal.
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
(a) NMI and INTWDT2 request signals generated at the same time
The pending INTWDT2 request signal is acknowledged after the non-maskable interrupt
Note Execute the initialization routine to restart the processing.
NMI and
(generated simultaneously)
INTWDT2 requests
User’s Manual U18953EJ5V0UD
Main routine
System reset
INTWDT2 servicing
Note
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