UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 59

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2.2
the system register numbers listed below.
Register
Number
21 to 31
System
6 to 15
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
Remark
16
17
18
19
20
0
1
2
3
4
5
System register set
2. These registers can be accessed only during the interval between the execution of the DBTRAP
Interrupt status saving register (EIPC)
Interrupt status saving register (EIPSW)
NMI status saving register (FEPC)
NMI status saving register (FEPSW)
Interrupt source register (ECR)
Program status word (PSW)
Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
CALLT execution status saving register (CTPC)
CALLT execution status saving register (CTPSW)
Exception/debug trap status saving register (DBPC)
Exception/debug trap status saving register (DBPSW)
CALLT base pointer (CTBP)
Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
program if multiple interrupts are enabled.
instruction or illegal opcode and DBRET instruction execution.
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
√: Can be accessed
×: Access prohibited
System Register Name
Table 3-2. System Register Numbers
Note 1
CHAPTER 3 CPU FUNCTION
Note 1
Note 1
User’s Manual U18953EJ5V0UD
Note 1
LDSR Instruction STSR Instruction
√
√
Operand Specification
Note 2
Note 2
√
√
√
√
×
√
×
√
√
√
×
√
√
Note 2
Note 2
√
√
√
√
√
√
×
√
√
√
×
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