UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 596
UPD70F3738GF-GAS-AX
Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3738GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(4) UARTC0 option control register 0 (UC0OPT0)
The UC0OPT0 register is an 8-bit register used to control SBF transmission/reception in the LIN
communication format and the level of the transmission/reception signals for the UARTC0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
UC0OPT0
After reset: 14H
Caution Do not set the UC0SRT and UC0STT bits (to 1) during SBF reception
• This bit indicates whether SBF (Sync Brake Field) is received in LIN communication.
• When an SBF reception error occurs, the UC0SRF bit remains 1 and SBF reception
• The UC0SRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and is always 0
• For SBF reception, set the UC0SRT bit (to 1) to enable SBF reception.
• Set the UC0SRT bit after setting the UC0PWR bit and UC0RXE bit to 1.
• This is the SBF transmission trigger bit during LIN communication, and is always 0
• Setting this bit to 1 triggers SBF transmission.
• Set the UC0STT bit after setting the UC0PWR bit and UC0TXE bit to 1.
UC0SRF
UC0SRT
UC0SRF
UC0STT
is started again.
when read.
when read.
<7>
0
1
0
1
0
1
The UC0CTL0.UC0PWR bit or the UC0CTL0.UC0RXE bit is set to 0,
or SBF reception ends normally.
During SBF reception
SBF reception trigger
SBF transmission trigger
UC0SRT UC0STT UC0SLS2 UC0SLS1 UC0SLS0 UC0TDL UC0RDL
R/W
(UC0SRF bit = 1).
6
Address: FFFFFAA3H
User’s Manual U18953EJ5V0UD
5
SBF transmission trigger
4
SBF reception trigger
SBF reception flag
−
−
3
2
PD70F3792, 70F3793)
1
0
(1/2)
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