UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 666

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

664
INTCBnT signal
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device
(5) When the serial clock is input, output the transmit data from the SOBn pin in synchronization with the
(6) When transfer of the transmit data from the CBnTX register to the shift register is completed and
(7) To continue transmission, repeat the above steps from (4) after the INTCBnT signal is generated.
(8) When the serial clock is input following completion of the transmission of the transfer data length set
(9) When transfer of the transmit data from the CBnTX register to the shift register is completed and
(10) When the number of clock cycles of the transfer data length set by the CBnCTL2 register is input
(11) To disable transmission, clear the CBnCTL0.CBnPWR and CBnCTL0.CBnTXE bits to 0 after
Caution In continuous transmission mode, the reception complete interrupt request signal
Remark
CBnTSF bit
SCKBn pin
Figure 18-24. Continuous Transfer Mode Operation Timing (Slave Mode, Transmission Mode)
SOBn pin
external clock (SCKBn), and slave mode.
transfer mode at the same time as enabling the operation of the communication clock (f
waits for serial clock input.
serial clock.
writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
by the CBnCTL2 register, continuous transmission is started.
writing to the CBnTX register is enabled, the INTCBnT signal is generated.
transmission with the current transmission, do not write to the CBnTX register.
without writing to the CBnTX register, clear the CBnTSF bit to 0 to end transmission.
confirming that the CBnTSF bit is set to 0.
(INTCBnR) is not generated.
n = 0 to 4
(1)
(2)
(3)
(4)
(5)
Bit 7
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
(6)
Bit 6
Bit 5
Bit 4 Bit 3
(7)
User’s Manual U18953EJ5V0UD
Bit 2
Bit 1
Bit 0
(8)
Bit 7
(9)
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
To end continuous
Bit 1
CCLK
(10)
Bit 0
).
CCLK
(11)
) =