UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 257

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.4.1
at a specified interval. Setting the TPnCE bit to 1 can also start the timer, which then outputs a square wave whose
half cycle is equal to the interval from the TOPn0 pin.
the interrupt mask flag (TPnCCMK1).
In the interval timer mode, setting the TPnCTL0.TPnCE bit to 1 generates an interrupt request signal (INTTPnCC0)
Usually, the TPnCCR1 register is not used in the interval timer mode. Mask interrupts from this register by setting
Remarks 1. For how to set the TOPn0 pin, see Table 7-2 Pins Used by TMPn and Table 4-15 Settings When
Interval timer mode (TPnMD2 to TPnMD0 bits = 000)
(CCR0 buffer register)
INTTPnCC0 signal
Remark
Remark
Count clock
TPnCCR0 register
TOPn0 pin output
2. For how to enable the INTTPnCC0 interrupt signal, see CHAPTER 21 INTERRUPT SERVICING/
3. n = 0 to 5
selection
16-bit counter
Pins Are Used for Alternate Functions.
EXCEPTION PROCESSING.
TPnCE bit
FFFFH
n = 0 to 5
n = 0 to 5
0000H
TPnCE bit
Figure 7-7. Basic Timing of Operation in Interval Timer Mode
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 7-6. Configuration of Interval Timer
Interval (D
User’s Manual U18953EJ5V0UD
D
0
0
+ 1) Interval (D
CCR0 buffer register
TPnCCR0 register
16-bit counter
Clear
Match signal
D
0
0
+ 1) Interval (D
D
0
D
0
0
+ 1) Interval (D
controller
Output
INTTPnCC0 signal
D
0
0
+ 1)
TOPn0 pin
255

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