UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 419

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TQ0IOC2
TQ0OPT0
(e) TMQ0 I/O control register 2 (TQ0IOC2)
(f) TMQ0 option register 0 (TQ0OPT0)
(g) TMQ0 counter read buffer register (TQ0CNT)
(h) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
The value of the 16-bit counter can be read by reading this register.
These registers function as capture registers or compare registers according to the setting of the
TQ0OPT0.TQ0CCSm bit.
When the registers function as capture registers, they store the value of the 16-bit counter when it is
detected that a valid edge has been input to the TIQ0m pin, after which the INTTQ0CCm signal is
generated.
When the registers function as compare registers and when the TQ0CCRm register is set to D
INTTQ0CCm signal is generated the when the counter reaches (D
TOQ0m pin is inverted.
Remark
TQ0CCS3
0/1
0
TQ0CCS2
m = 0 to 3
Figure 8-55. Register Settings in Free-Running Timer Mode (3/3)
0/1
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0CCS1
0/1
0
TQ0CCS0
0/1
0
User’s Manual U18953EJ5V0UD
TQ0EES1
0/1
0
TQ0EES0 TQ0ETS1 TQ0ETS0
0/1
0
0
0
m
TQ0OVF
+ 1), and the output signal of the
0/1
0
These bits select the valid edge
of the external event count input.
Overflow flag
Specifies whether TQ0CCR0
register is used for capture
or compare.
Specifies whether TQ0CCR1
register is used for capture
or compare.
Specifies whether TQ0CCR2
register is used for capture
or compare.
Specifies whether TQ0CCR3
register is used for capture
or compare.
m
, the
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