UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 868

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.3 Register to Check Reset Source
reset source flag register (RESF) immediately after a reset ends.
866
The V850ES/JG3-L has four reset sources. The source of the reset that occurred can be checked by using the
(1) Reset source flag register (RESF)
Note The value of the RESF register is cleared to 00H when a reset is executed via the RESET pin. When a
Caution Only “0” can be written to each bit of this register. If writing “0” conflicts with setting the flag
The RESF register is a special register that can be written only in a combination of specific sequences (see
3.4.7 Special registers).
The RESF register indicates the source that generated a reset signal.
This register is read or written in 8-bit or 1-bit units.
RESET pin input clears this register to 00H. The default value differs if the source of the reset is other than the
RESET pin signal.
reset is executed by watchdog timer 2 (WDT2), the low-voltage detector (LVI), or the clock monitor
(CLM), the reset flags of this register (WDT2RF bit, CLMRF bit, and LVIRF bit) are set. However, other
sources are retained.
(occurrence of reset), setting the flag takes precedence.
RESF
After reset: 00H
WDT2RF
CLMRF
LVIRF
0
1
0
1
0
1
0
Note
Not generated
Generated
Not generated
Generated
Not generated
Generated
R/W
0
CHAPTER 24 RESET FUNCTION
User’s Manual U18953EJ5V0UD
Address: FFFFF888H
0
Reset signal from WDT2
Reset signal from CLM
Reset signal from LVI
WDT2RF
0
0
CLMRF
LVIRF