UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 591

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) UARTC0 control register 0 (UC0CTL0)
(2) UARTC0 control register 1 (UC0CTL1)
(3) UARTC0 control register 2 (UC0CTL2)
(4) UARTC0 option control register 0 (UC0OPT0)
(5) UARTC0 option control register 1 (UC0OPT1)
(6) UARTC0 status register (UC0STR)
(7) UARTC0 receive shift register
(8) UARTC0 receive data register (UC0RX)
(9) UARTC0 transmit shift register
(10) UARTC0 transmit data register (UC0TX)
The UC0CTL0 register is an 8-bit register used to specify the operation of UARTC0.
The UC0CTL1 register is an 8-bit register used to select the base clock (f
The UC0CTL2 register is an 8-bit register used with the UC0CTL1 register to generate the baud rate for
UARTC0.
The UC0OPT0 register is an 8-bit register used to control SBF transmission/reception in the LIN
communication format and the level of the transmission/reception signals for the UARTC0.
The UC0OPT1 register is an 8-bit register used to control 9-bit length serial transfer for the UARTC0.
The UC0STR register is an 8-bit register that indicates the contents of a reception error. Each one of the
reception error flags is set (to 1) upon the occurrence of a reception error.
This is a shift register used to convert the serial data input to the RXDC0 pin into parallel data. Upon reception
of 1-character data and detection of the stop bit, the receive data is transferred to the UC0RX register.
This register cannot be manipulated directly.
The UC0RX register is an 8-bit buffer register that holds receive data.
In the reception enabled status, receive data is transferred from the UARTC0 receive shift register to the
UC0RX register in synchronization with the completion of shift-in processing of 1 character.
Transfer to the UC0RX register also causes the reception complete interrupt request signal (INTUC0R) to be
output.
The transmit shift register is a shift register used to convert the parallel data transferred from the UC0TX
register into serial data.
When 1-character data is transferred from the UC0TX register, the shift register data is output from the TXDC0
pin.
This register cannot be manipulated directly.
The UC0TX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the
UC0TX register. When data can be written to the UC0TX register (when 1-character data is transferred from
the UC0TX register to the UARTC0 transmit shift register), the transmission enable interrupt request signal
(INTUC0T) is generated.
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
User’s Manual U18953EJ5V0UD
UCLK
PD70F3792, 70F3793)
) for UARTC0.
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