UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 370

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

368
(f) TMQ0 capture/compare register 0 (TQ0CCR0)
(g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
When the TQ0CCR0 register is set to D
signal (INTTQ0CC0) is generated when the number of external events reaches (D
The TQ0CCR1 to TQ0CCR3 registers are not usually used in the external event count mode. However,
because the set values of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3
buffer registers and a compare match interrupt request signal (INTTQ0CC1 to INTTQ0CC3) is
generated when the value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer
registers, interrupts from these registers must be masked by setting the interrupt mask flags
(TQ0CCMK1 to TQ0CCMK3).
Cautions 1. Do not set the TQ0CCR0 register to 0000H in the external event count mode.
Remark
2. Timer output cannot be used in the external event count mode. When using the
3. When an external clock is used as the count clock, the external clock can be input
TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used
in the external event count mode.
Figure 8-19. Register Settings in External Event Count Mode (2/2)
timer output based on the input of an external event count, first set the operating
mode to interval mode, and then specify “operation enabled” for the external event
count input (by setting the TQ0CTL1.TQ0MD2 to TQ0MD0 bits to 0, 0, 0 and setting
the TQ0CTL1.TQ0EEE bit to 1). (For details, see 8.4.1 (3) Operation of interval timer
based on input of external event count.)
only from the TIQ00 pin. At this time, set the TQ0IOC1.TQ0IS1 and TQ0IOC1.TQ0IS0
bits to 0, 0 (capture trigger input (TIQ00 pin): no edge detection).
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U18953EJ5V0UD
0
, the counter is cleared and a compare match interrupt request
0
+ 1).