UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 557

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
16.4 Registers
(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(n = 0 to 5)
UAnCTL0
After reset: 10H
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Note
UAnPWR
UAnPWR
UAnRXE
The UARTAn operation is controlled by the UAnPWR bit. The TXDAn pin output
is fixed to high level by clearing the UAnPWR bit to 0 (fixed to low level if
UAnOPT0.UAnTDL bit = 1).
UAnTXE
• To start transmission, set the UAnPWR bit to 1 and then set the UAnTXE bit to 1.
• To initialize the transmission unit, clear the UAnTXE bit to 0, wait for two cycles of
• When UARTAn operation is enabled (UAnPWR bit = 1) and the UAnTXE bit is set
• To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1.
• To initialize the reception unit, clear the UAnRXE bit to 0, wait for two cycles of
• When UARTAn operation is enabled (UAnPWR bit = 1) and the UAnRXE bit is set
To stop transmission, clear the UAnTXE bit to 0 and then UAnPWR bit to 0.
the base clock, and then set the UAnTXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 16.7 (1) (a) Base clock).
to 1, transmission is enabled after at least two cycles of the base clock (f
elapsed.
To stop reception, clear the UAnRXE bit to 0 and then UAnPWR bit to 0.
the base clock, and then set the UAnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 16.7 (1) (a) Base clock).
to 1, reception is enabled after at least two cycles of the base clock (f
elapsed. If a start bit is received before reception is enabled, the start bit is
ignored.
<7>
0
1
0
1
0
1
μ
Disable UARTAn operation (UARTAn reset asynchronously)
Enable UARTAn operation
Disable transmission operation
Enable transmission operation
Disable reception operation
Enable reception operation
R/W
UAnTXE UAnRXE UAnDIR
PD70F3792, 70F3793 only
<6>
Address: UA0CTL0 FFFFFA00H, UA1CTL0 FFFFFA10H,
User’s Manual U18953EJ5V0UD
<5>
UA2CTL0 FFFFFA20H, UA3CTL0 FFFFFA30H
UA4CTL0 FFFFFA40H
Transmission operation enable
Reception operation enable
UARTAn operation control
<4>
UAnPS1 UAnPS0
3
Note
, UA5CTL0 FFFFFA50H
2
UAnCL
1
UCLK
UCLK
) have
UAnSL
Note
) have
0
,
Note
(1/2)
555