UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 552

no-image

UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
550
(1) UARTAn control register 0 (UAnCTL0)
(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
(4) UARTAn option control register 0 (UAnOPT0)
(5) UARTAn status register (UAnSTR)
(6) UARTAn receive shift register
(7) UARTAn receive data register (UAnRX)
(8) UARTAn transmit shift register
(9) UARTAn transmit data register (UAnTX)
The UAnCTL0 register is an 8-bit register used to specify the operation of UARTAn.
The UAnCTL1 register is an 8-bit register used to select the base clock (f
The UAnCTL2 register is an 8-bit register used with the UAnCTL1 register to generate the baud rate for
UARTAn.
The UAnOPT0 register is an 8-bit register used to control SBF transmission/reception in the LIN
communication format and the level of the transmission/reception signals for the UARTAn.
The UAnSTR register is an 8-bit register that indicates the contents of a reception error. Each one of the
reception error flags is set (to 1) upon the occurrence of a reception error.
This is a shift register used to convert the serial data input to the RXDAn pin into parallel data. Upon reception
of 1-character data and detection of the stop bit, the receive data is transferred to the UAnRX register.
This register cannot be manipulated directly.
The UAnRX register is an 8-bit buffer register that holds receive data.
In the reception enabled status, receive data is transferred from the UARTAn receive shift register to the
UAnRX register in synchronization with the completion of shift-in processing of 1 character.
Transfer to the UAnRX register also causes the reception complete interrupt request signal (INTUAnR) to be
output.
The transmit shift register is a shift register used to convert the parallel data transferred from the UAnTX
register into serial data.
When 1-character data is transferred from the UAnTX register, the shift register data is output from the TXDAn
pin.
This register cannot be manipulated directly.
The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the
UAnTX register. When data can be written to the UAnTX register (when 1-character data is transferred from
the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal
(INTUAnT) is generated.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
User’s Manual U18953EJ5V0UD
UCLK
) for UARTAn.

Related parts for UPD70F3738GF-GAS-AX