UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 848

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.6.3 Re-setting after release of low-voltage STOP mode
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(1) If low-voltage STOP mode is released by interrupt
(2) If low-voltage STOP mode is released by reset
The status after the low-voltage STOP mode has been released is as follows.
• Regulator: Automatically returns to the normal level.
• REGOVL0 register = 01H (low-voltage STOP mode): Value described in 23.6.1 (1) <5> is retained.
• REGPR register = 00H (protection data): Value described in 23.6.1 (1) <6> is retained.
(a) To continuously use the REGOVL0 register = 01H (low-voltage STOP mode), the other registers do not
(b) Follow this procedure when returning the REGOVL0 register = 00H.
The CPU shifts to the normal operation mode immediately after the reset ends, and the REGOVL0 register is
initialized to 00H and the REGPR register to 00H (protection data).
stabilization time that follows immediately after a reset ends by setting the option byte. For details, see
CHAPTER 29 OPTION BYTE.
Caution Interrupt requests that are set to 1 (disabled) by the PSC.NMI1M, PSC.NMI0M, and
The oscillation stabilization time specified by the OSTS register is secured.
Be sure to observe the above sequence.
have to be set again.
<1> Disable the DMA.
<2> • Disable the maskable interrupt by the DI instruction.
<3> Write C9H (enabling data) to the REGPR register.
<4> Write 00H to the REGOVL0 register.
<5> Write 00H (protection data) to the REGPR register.
<6> As necessary, enable the maskable interrupt, NMI interrupt, or INTWDT2 interrupt by enabling DMA
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (stop watchdog timer 2 or set a
or the EI instruction (restore the settings <1> and <2> above).
PSC.INTM bits are invalid and cannot release the low-voltage STOP mode.
mode other than the INTWDT2 mode. Create a status in which the INTWDT2 signal is not
generated immediately after watchdog timer 2 has been cleared).
CHAPTER 23 STANDBY FUNCTION
User’s Manual U18953EJ5V0UD
Be sure to secure the oscillation