UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 882

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
880
Clock monitor status
Internal reset signal
(1) Operation when main clock oscillation is stopped (CLME bit = 1)
(2) Clock monitor status after RESET input
Internal oscillator
RESF.CLMRF bit
Internal oscillator
CLM.CLME bit
If oscillation of the main clock is stopped when the CLME bit is 1, an internal reset signal is generated as
shown in Figure 25-2.
RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When the CLME bit is set
to 1 by software after the normal operation is started, monitoring is started.
CPU operation
(active-low)
Main clock
Main clock
RESET
CLME
clock
clock
(CLM.CLME Bit = 1 Is Set After RESET Is Input and Normal Operation Is Started)
Monitoring
Figure 25-2. Reset Period Due to Stoppage of Main Clock Oscillation
operation
Normal
Figure 25-3. Clock Monitor Status After RESET Input
Reset
CHAPTER 25 CLOCK MONITOR
User’s Manual U18953EJ5V0UD
stabilization time
Clock supply
Oscillation
Four internal oscillator clocks
stopped
Monitoring stopped
Normal operation
Set to 1 by software
Monitoring

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