UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 346

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(10) TMQ0 capture/compare register 3 (TQ0CCR3)
The TQ0CCR3 register can be used as a capture register or a compare register depending on the mode.
This register can be selected as a capture register or a compare register only in the free-running timer mode,
according to the setting of the TQ0OPT0.TQ0CCS3 bit. In the pulse width measurement mode, the TQ0CCR3
register can be used only as a capture register. In any other mode, this register can be used only as a
compare register.
The TQ0CCR3 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TQ0CCR3 register is prohibited in the following statuses. Moreover, if the
(a) Function as compare register
(b) Function as capture register
The TQ0CCR3 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1.
The set value of the TQ0CCR3 register is transferred to the CCR3 buffer register. When the value of the
16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal
(INTTQ0CC3) is generated. If TOQ03 pin output is enabled at this time, the output of the TOQ03 pin is
inverted (For details, see the descriptions of each operating mode.).
When the TQ0CCR3 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQ0CCR3 register if the valid edge of the capture trigger input pin
(TIQ03 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TQ0CCR3 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQ03 pin) is detected.
Even if the capture operation and reading the TQ0CCR3 register conflict, the correct value of the
TQ0CCR3 register can be read.
TQ0CCR3
system is in the wait status, the only way to cancel the wait status is to execute a reset. For
details, see 3.4.9 (1) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and main clock oscillation is stopped
• When the CPU operates on the internal oscillator clock
After reset: 0000H
15
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
14
13
R/W
12
User’s Manual U18953EJ5V0UD
11
Address:
10
9
FFFFF54CH
8
7
6
5
4
3
2
1
0