UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 660

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

658
SIBn pin capture
INTCBnR signal
CBnSCE bit
CBnTSF bit
SCKBn pin
SOBn pin
SIBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and
(5) When reception is started, output the serial clock to the SCKBn pin, and capture the receive data of
(6) When reception is completed, the reception complete interrupt request signal (INTCBnR) is generated,
(7) Because the CBnCTL0.CBnSCE bit was 1 when communication ended, the next communication is
(8) To end continuous reception with the current reception, clear the CBnSCE bit to 0.
(9) Read the CBnRX register.
(10) When reception is completed, the INTCBnR signal is generated and reading receive data from the
(11) Read the CBnRX register.
(12) To disable reception, clear the CBnCTL0.CBnPWR and CBnCTL0.CBnRXE bits to 0 after confirming
Remark
timing
Figure 18-20. Continuous Transfer Mode Operation Timing (Master Mode, Reception Mode)
f
mode at the same time as enabling the operation of the communication clock (f
reception is started.
the SIBn pin in synchronization with the serial clock.
and reading receive data from the CBnRX register is enabled.
started immediately.
CBnRX register is enabled. If the CBnSCE bit is set to 0 before communication is complete, stop the
serial clock output to the SCKBn pin and clear the CBnTSF bit to 0 to end the receive operation.
that the CBnTSF bit is 0.
XX
L
/2, and master mode.
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
Bit 7 Bit 6
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5 Bit 4
Bit 3 Bit 2
User’s Manual U18953EJ5V0UD
Bit 1
(6) (7) (8) (9)
Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1
(10)
Bit 0
CCLK
).
(11) (12)
CCLK
) =