UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 373

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Notes on rewriting TQ0CCR0 register
When rewriting the value of the TQ0CCR0 register to a smaller value, stop counting first and then change
the set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
If the value of the TQ0CCR0 register is changed from D
but less than D
register has been rewritten. Consequently, the value that is compared with the 16-bit counter value is D
Because the counter value has already exceeded D
overflows, and then increments up again from 0000H.
INTTQ0CC0 signal is generated.
Therefore, the INTTQ0CC0 signal may not be generated at the valid edge of the external event count
signal when the external event count is “(D
generated at the valid edge of the external event count signal when the external event count is “(10000H +
D
2
+ 1)”.
(CCR0 buffer register)
INTTQ0CC0 signal
TQ0CCR0 register
16-bit counter
TQ0CE bit
1
, the TQ0CCR0 register value is transferred to the CCR0 buffer register as soon as the
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Figure 8-22. Rewriting TQ0CCR0 Register
External event
count signal
interval (1)
(D
User’s Manual U18953EJ5V0UD
1
+ 1)
D
1
1
D
1
+ 1)” or “(D
External event count signal
interval (NG)
(10000H + D
D
2
2
, however, the 16-bit counter increments up to FFFFH,
D
2
1
1
+ 1)” as originally expected, but instead may be
to D
2
When the counter value matches D
+ 1)
2
while the counter value is greater than D
D
2
D
2
External event
count signal
interval (2)
(D
D
2
+ 1)
2
2
, the
371
2
.
2