UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 673

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.6.13 Reception errors
the reception complete interrupt request signal (INTCBnR) is generated again if the next receive operation is
completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag
(CBnSTR.CBnOVE) is set to 1.
reception error occurs, the INTCBnR signal is generated again upon completion of the next reception if the CBnRX
register is not read.
of the next receive data is sampled after the INTCBnR signal is generated.
SIBn pin capture
When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode,
If an overrun error occurs, the previous receive data is lost because the CBnRX register is updated. Even if a
An overrun error occurs if reading the CBnRX register has not been completed half a clock cycle before the last bit
INTCBnR signal
CBnRX register
CBnRX register
Shift register
CBnOVE bit
read signal
SCKBn pin
(1) Start of continuous transfer
(2) Completion of the first transfer
(3) The CBnRX register cannot be read until half a clock cycle before the completion of the second
(4) An overrun error occurs, the reception complete interrupt request signal (INTCBnR) is generated, and
Remark
SIBn pin
timing
transfer.
the overrun error flag (CBnSTR.CBnOVE) is set to 1. The receive data is overwritten.
n = 0 to 4
(1)
01H
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
02H
05H 0AH 15H 2AH 55H AAH 00H 01H 02H 05H 0AH 15H 2AH 55H
Figure 18-29. Overrun Error Timing
User’s Manual U18953EJ5V0UD
(2)
AAH
(3)
(4)
55H
671