UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 636

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

634
Note These bits can only be rewritten when the CBnPWR bit is 0.
CBnTMS
CBnDIR
[In single transfer mode]
• In this mode, the reception complete interrupt (INTCBnR) occurs upon completion
• After the reception complete interrupt (INTCBnR) occurs, writing/reading the next
• The next communication does not start even if the next transmit/receive data is
[In continuous transfer mode]
• In this mode and with transmission enabled (CBnTXE bit = 1), the transmission
• Writing the next transmit data becomes possible after INTCBnT occurs. If new
• If reception-only is specified (CBnTXE bit = 0, CBnRXE bit = 1), the next
of communication. The transmission enable interrupt (INTCBnT) does not occur
even if transmission is enabled (CBnTXE bit = 1).
transmit/receive data triggers the next communication.
written/read during the preceding communication (CBnSTR.CBnTSF bit = 1).
enable interrupt (INTCBnT) occurs when writing the next transmit data becomes
possible. With reception enabled (CBnRXE bit = 1), the reception complete
interrupt (INTCBnR) occurs upon completion of transfer.
data is written at this time, continuous transfer can be performed.
transmission starts immediately after INTCBnR has occurred, regardless of the
progress of reading the CBnRX register. Be sure to read receive data immediately
after INTCBnR has occurred. If receive data is not read before the next INTCBnR
occurs, an overrun error will occur (CBnSTR.CBnOVE bit = 1).
0
1
0
1
Note
Note
However, the values of these bits can be changed to 0 or 1 at the
same time the CBnPWR bit is set.
Single transfer mode
Continuous transfer mode
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
MSB-first transfer
LSB-first transfer
Specification of transfer direction mode (MSB/LSB)
User’s Manual U18953EJ5V0UD
Transfer mode specification
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