UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 191
UPD70F3738GF-GAS-AX
Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3738GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.5.2
the BSC register.
odd addresses.
The external memory area of the V850ES/JG3-L is selected by memory blocks 0 to 3.
The bus size of each external memory area selected by memory block n can be set (to 8 bits or 16 bits) by using
If a 16-bit bus width is specified, the lower 8 bits are used for even addresses and the higher 8 bits are used for
(1) Bus size configuration register (BSC)
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not
This register controls the bus width of the memory block space.
This register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Bus size setting function
Memory
block n signal
After reset: 5555H
BSC
access an external memory area until the initial settings of the BSC register are complete.
Note If a 16-bit bus width is specified, writing can be controlled in 8-bit units
Caution Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15,
BSn0
15
0
0
0
1
7
Memory block 3
via two control pins (WR0 and WR1) but reading can be controlled
only in 16-bit units because reading is controlled via one control pin
(RD). In the V850ES/JG3-L, however, unnecessary data is ignored,
so byte access is possible.
8 bits
16 bits
13, 11, 9, 7, 5, 3, and 1 to “0”.
BS30
14
1
6
R/W
Data bus width of memory block n space (n = 0 to 3)
CHAPTER 5 BUS CONTROL FUNCTION
Note
Address: FFFFF066H
13
User’s Manual U18953EJ5V0UD
0
5
0
Memory block 2
BS20
12
1
4
11
0
3
0
Memory block 1
BS10
10
1
2
9
0
1
0
Memory block 0
BS00
1
8
0
189
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