UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 495

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4 Operation
timer 2, write the operation mode setting and the loop detection time interval to the WDTM2 register using an 8-bit
memory manipulation instruction. After this, the operation of watchdog timer 2 cannot be stopped.
interval.
After the count operation has started, write ACH to WDTE within the loop detection time interval.
(WDT2RES) or a non-maskable interrupt request signal (INTWDT2) is generated, depending on the values of the
WDTM2.WDM21 and WDTM2.WDM20 bits.
immediately after a reset ends or after a standby is released, no internal reset will occur and the CPU clock will switch
to the internal oscillator clock.
set, see 21.2.2 (2) From INTWDT2 signal.
(2) Watchdog timer enable register (WDTE)
Watchdog timer 2 automatically starts in the reset mode immediately after a reset.
The WDTM2 register can be written to only once immediately after a reset using byte access. To use watchdog
The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again.
If the loop detection time interval expires without ACH being written to the WDTE register, a reset signal
When the WDTM2.WDM21 bit is set to 1 (reset mode), if watchdog timer 2 overflows during oscillation stabilization
To not use watchdog timer 2, write 00H to the WDTM2 register.
For details of the non-maskable interrupt servicing that occurs when the non-maskable interrupt request mode is
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
The counter of watchdog timer 2 is cleared and counting is restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units. (When a 1-bit memory manipulation instruction is
executed on the WDTE register, an overflow signal is forcibly generated.)
Reset sets this register to 9AH.
2. To intentionally generate an overflow signal, write a value other than “ACH” to the WDTE
3. The read value of the WDTE register is “9AH” (which differs from the written value “ACH”).
WDTE
After reset: 9AH
forcibly output.
register once, or write data to the WDTM2 register twice.
However, when watchdog timer 2 is set to “stop operation”, an overflow signal is not
generated even if a value other than “ACH” is written to the WDTE register once, or data is
written to the WDTM2 register twice.
R/W
CHAPTER 12 WATCHDOG TIMER 2
Address: FFFFF6D1H
User’s Manual U18953EJ5V0UD
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