UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 18

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 19 I
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) ................................................................... 757
16
19.1 Mode Switching of I
19.2 Features ...................................................................................................................................681
19.3 Configuration...........................................................................................................................682
19.4 Registers ..................................................................................................................................686
19.5 I
19.6 I
19.7 I
19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control .........................732
19.9 Address Match Detection Method .........................................................................................734
19.10 Error Detection ........................................................................................................................734
19.11 Extension Code .......................................................................................................................734
19.12 Arbitration ................................................................................................................................735
19.13 Wakeup Function ....................................................................................................................736
19.14 Communication Reservation .................................................................................................737
19.15 Cautions ...................................................................................................................................742
19.16 Communication Operations ...................................................................................................743
19.17 Timing of Data Communication .............................................................................................751
20.1 Features ...................................................................................................................................757
20.2 Configuration...........................................................................................................................758
20.3 Registers ..................................................................................................................................760
20.4 Transfer Sources and Destinations ......................................................................................768
20.5 Transfer Modes........................................................................................................................768
20.6 Transfer Types.........................................................................................................................769
19.1.1
19.1.2
19.1.3
19.5.1
19.6.1
19.6.2
19.6.3
19.6.4
19.6.5
19.6.6
19.6.7
19.7.1
19.7.2
19.7.3
19.7.4
19.7.5
19.7.6
19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .........................737
19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) ........................741
19.16.1 Master operation in single master system .................................................................................744
19.16.2 Master operation in multimaster system ....................................................................................745
19.16.3 Slave operation..........................................................................................................................748
2
2
2
C Bus Mode Functions .........................................................................................................703
C Bus Definitions and Control Methods .............................................................................704
C Interrupt Request Signals (INTIICn).................................................................................712
2
C BUS .......................................................................................................................... 678
UARTA2 and I
CSIB0 and I
UARTA1 and I
Pin configuration........................................................................................................................703
Start condition............................................................................................................................704
Addresses..................................................................................................................................705
Transfer direction specification ..................................................................................................706
ACK ...........................................................................................................................................707
Stop condition............................................................................................................................708
Wait state ..................................................................................................................................709
Wait state cancellation method..................................................................................................711
Master device operation ............................................................................................................712
Slave device operation (when receiving slave address data (address match))..........................715
Slave device operation (when receiving extension code) ..........................................................719
Operation without communication .............................................................................................723
Operation when arbitration loss occurs (operation as slave after arbitration loss) .....................723
Operation when arbitration loss occurs (no communication after arbitration loss) .....................725
2
C01 mode switching ..............................................................................................679
2
2
2
C Bus and Other Serial Interfaces......................................................678
C00 mode switching ..........................................................................................678
C02 mode switching ..........................................................................................680
User’s Manual U18953EJ5V0UD