UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 558

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

556
(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
For details, see 16.7 (2) UARTAn control register 1 (UAnCTL1).
For details, see 16.7 (3) UARTAn control register 2 (UAnCTL2).
Remark
• This register is rewritten only when the UAnPWR bit is 0 or the UAnTXE bit and the
• If “Reception with 0 parity” is selected during reception, a parity check is not performed.
• When transmission and reception are performed in the LIN format, clear the
• This register can be rewritten only when the UAnPWR bit is 0 or the UAnTXE bit
• When transmission and reception are performed in the LIN format, set the UAnCL
This register can be rewritten only when the UAnPWR bit is 0 or the UAnTXE bit and
the UAnRXE bit are 0.
• This register can be rewritten only when the UAnPWR bit is 0 or the UAnTXE bit
• When transmission and reception are performed in the LIN format, set the UAnDIR
UAnPS1
UAnDIR
UAnCL
UAnSL
UAnRXE bit are 0.
Therefore, the UAnSTR.UAnPE bit is not set.
UAnPS1 and UAnPS0 bits to 00.
and the UAnRXE bit are 0.
bit to 1.
and the UAnRXE bit are 0.
bit to 1.
0
1
0
1
0
1
0
0
1
1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
7 bits
8 bits
1 bit
2 bits
MSB first
LSB first
For details of parity, see 16.6.6 Parity types and operations.
UAnPS0
Specification of data character length of 1 frame of transmit/receive data
0
1
0
1
Parity selection during transmission Parity selection during reception
No parity output
0 parity output
Odd parity output
Even parity output
Specification of length of stop bit for transmit data
User’s Manual U18953EJ5V0UD
Data transfer order
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
(2/2)