UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 194

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

192
15
Halfword
data
(3) Halfword access (16 bits)
<1> Access to even address (2n)
8
7
0
15
(a) 16-bit data bus width
(b) 8-bit data bus width
8
7
0
Halfword
data
First access
16-bit data is transmitted/received via a 16-bit bus. Therefore, if an even address is specified, the lower
and higher bytes of the external data bus address are accessed at the same time. If an odd address is
specified, the lower byte of the data is transmitted/received to/from an odd address via the higher byte of
the external data bus address in the first access. In the second access, the higher byte of the data is
transmitted/received to/from an odd address via the lower byte of the external data bus address.
16-bit data is transmitted/received via an 8-bit bus. Therefore, the data is transmitted/received in two
accesses.
lower/higher byte of the external bus address.
<1> Access to even address (2n)
7
0
External
data bus
15
External
data bus
8
7
0
2n
Address
The lower/higher byte of the data is transmitted/received to/from the corresponding
2n + 1
2n
Address
15
Halfword
data
8
7
0
Second access
CHAPTER 5 BUS CONTROL FUNCTION
7
0
External
data bus
User’s Manual U18953EJ5V0UD
15
Halfword
data
8
7
0
2n + 1
Address
First access
15
External
data bus
8
7
0
<2> Access to odd address (2n + 1)
Halfword
data
15
8
7
0
2n + 1
2n
Address
First access
<2> Access to odd address (2n + 1)
External
data bus
7
0
Address
2n + 1
15
8
7
0
Halfword
data
15
Halfword
data
8
7
0
Second access
15
Second access
8
7
0
External
data bus
7
0
External
data bus
2n + 2
Address
2n + 2
Address