ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 87

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

11. Timer/Counter0 and Timer/Counter1 Prescalers
11.1
11.2
11.3
7647G–AVR–09/11
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Coun-
ters can have different prescaler settings. The description below applies to both
Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
used as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implica-
tions for situations where a prescaled clock is used. One example of prescaling artifacts
occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1
to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
11-1
detector logic. The registers are clocked at the positive edge of the internal system clock
(
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 11-1. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the Tn/T0 pin to the counter is updated.
CLK_I/O
clk
I/O
T1
). The latch is transparent in the high period of the internal system clock.
/clk
shows a functional equivalent block diagram of the Tn/T0 synchronization and edge
Tn
/256, or f
clk
T0
I/O
). The Tn pin is sampled once every system clock cycle by the pin synchronization
CLK_I/O
D
LE
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be
Atmel ATmega16/32/64/M1/C1
T1
/clk
T
0
pulse for each positive (CSn2:0 = 7) or negative
D
Q
Edge Detector
CLK_I/O
/8, f
Tn_sync
(To Clock
Select Logic)
CLK_I/O
Figure
/64,
87