ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 85
ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
- Current page: 85 of 367
- Download datasheet (7Mb)
10.2.4
10.2.5
7647G–AVR–09/11
Pin Change Interrupt Flag Register - PCIFR
Pin Change Mask Register 3 – PCMSK3
• Bit 7..4 - Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 3 - PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT26..24 pin triggers an interrupt request, PCIF3 becomes
set (one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes
set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 7..3 – Res: Reserved Bit
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 2..0 – PCINT26..24: Pin Change Enable Mask 26..24
Each PCINT26..24-bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT26..24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT23..24 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
7
0
-
R
7
–
0
R/W
6
0
-
R
6
–
0
R/W
5
0
-
R
5
–
0
Atmel ATmega16/32/64/M1/C1
R/W
4
0
-
R
4
–
0
R/W
PCIF3
3
0
-
R
3
0
PCINT26
PCIF2
R/W
R/W
2
0
2
0
PCINT25
PCIF1
R/W
R/W
1
0
1
0
PCINT24
PCIF0
R/W
R/W
0
0
0
0
PCMSK3
PCIFR
85
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