ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 84

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

10.2.2
10.2.3
84
Atmel ATmega16/32/64/M1/C1
External Interrupt Flag Register – EIFR
Pin Change Interrupt Control Register - PCICR
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 3..0 – INTF3 - INTF0: External Interrupt Flag 3 - 0
When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit INT3:0 in
EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
These flags are always cleared when INT3:0 are configured as a level interrupt.
• Bit 7..4 - Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 3 - PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT26..24 pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the
PCI3 Interrupt Vector. PCINT26..24 pins are enabled individually by the PCMSK3 Register.
• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the
PCI2 Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
R
R
5
–
0
5
–
0
R
4
–
0
R
4
–
0
INTF3
PCIE3
R/W
R
3
0
3
0
INTF2
PCIE2
R/W
R/W
2
0
2
0
INTF1
PCIE1
R/W
R/W
1
0
1
0
INTF0
PCIE0
R/W
R/W
0
0
0
0
7647G–AVR–09/11
PCICR
EIFR