ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 226

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

17.6.4
226
Atmel ATmega16/32/64/M1/C1
LIN Error Register - LINERR
• Bit 2 - LENIDOK: Enable Identifier Interrupt
• Bit 1 - LENTXOK: Enable Transmit Performed Interrupt
• Bit 0 - LENRXOK: Enable Receive Performed Interrupt
• Bit 7 - LABORT: Abort Flag
• Bit 6 - LTOERR: Frame_Time_Out Error Flag
• Bit 5 - LOVERR: Overrun Error Flag
• Bit 4 - LFERR: Framing Error Flag
• Bit 3 - LSERR: Synchronization Error Flag
Bit
Read/Write
Initial Value
– 1 = Error interrupt enabled.
– 0 = Identifier interrupt masked,
– 1 = Identifier interrupt enabled.
– 0 = Transmit performed interrupt masked,
– 1 = Transmit performed interrupt enabled.
– 0 = Receive performed interrupt masked,
– 1 = Receive performed interrupt enabled.
– 0 = No warning,
– 1 = LIN abort command occurred.
– 0 = No error,
– 1 = Frame_Time_Out error.
– 0 = No error,
– 1 = Overrun error.
– 0 = No error,
– 1 = Framing error.
– 0 = No error,
– 1 = Synchronization error.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
LABORT
R
7
0
LTOERR
R
6
0
LOVERR
R
5
0
LFERR
R
4
0
LSERR
R
3
0
LPERR
R
2
0
LCERR
R
1
0
LBERR
R
0
0
7647G–AVR–09/11
LINERR