ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 17

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

3.7
3.8
7647G–AVR–09/11
Instruction Execution Timing
Reset and Interrupt Handling
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
the chip. No internal clock division is used.
Figure 3-4
Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 3-4.
Figure 3-5
ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 3-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Inter-
rupt Enable bit in the Status Register in order to enable the interrupt. Depending on the
Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02
or BLB12 are programmed. This feature improves software security. See the section
Programming” on page 296
Register Operands Fetch
ALU Operation Execute
Total Execution Time
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
Result Write Back
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an
shows the parallel instruction fetches and instruction executions enabled by the
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
CPU
clk
CPU
for details.
CPU
T1
Atmel ATmega16/32/64/M1/C1
T1
, directly generated from the selected clock source for
T2
T2
T3
T3
T4
“Memory
T4
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