ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 227

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

17.6.5
17.6.6
7647G–AVR–09/11
LIN Bit Timing Register - LINBTR
LIN Baud Rate Register - LINBRR
• Bit 2 - LPERR: Parity Error Flag
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
• Bits 15:12 - Reserved Bits
• Bits 11:0 - LDIV[11:0]: Scaling of clk
Bit
Read/Write
Initial Value
Bit
Bit
Read/Write
Initial Value
be written to zero when LINBRR is written.
or UART baud rate.
– 0 = No error,
– 1 = Parity error.
– 0 = No error,
– 1 = Checksum error.
– 0 = no error,
– 1 = Bit error.
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
Gives the number of samples of a bit.
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
These bits are reserved for future use. For compatibility with future devices, they must
The LDIV value is used to scale the entering clk
LDISR
LDIV7
R/W
R/W
15
7
0
7
0
-
sample-time = (1 /
LDIV6
R/W
14
R
6
0
6
0
-
-
LDIV5
R/(W)
LBT5
R/W
13
5
1
5
0
-
Atmel ATmega16/32/64/M1/C1
i/o
LDIV4
R/(W)
LBT4
f
R/W
clk
12
4
0
4
0
-
Frequency
i/o
) x (LDIV[11..0] + 1)
LDIV11
R/(W)
LDIV3
LBT3
R/W
3
0
11
3
0
i/o
frequency to achieve appropriate LIN
R/(W)
LDIV10
LBT2
LDIV2
R/W
2
0
10
2
0
R/(W)
LBT1
LDIV1
LDIV9
R/W
1
0
1
9
0
LDIV0
LDIV8
R/(W)
LBT0
R/W
0
0
0
0
8
LINBRRH
LINBRRL
LINBTR
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