ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 250

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

18.9.6
18.10 Amplifier
250
Atmel ATmega16/32/64/M1/C1
Digital Input Disable Register 1– DIDR1
• Bit 6:0 – ADC10D..8D, ACMP0D, ACMP1D, ACMP3D, AMP0PD, AMP0ND, AMP1PD,
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When
an analog signal is applied to an analog pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
The ATmega16/32/64/M1/C1 features three differential amplified channels with programmable
5, 10, 20, and 40 gain stage.
Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a syn-
chronization signal called in this document the amplifier synchronization clock. To ensure an
accurate result, the amplifier input needs to have a quite stable input value during at least 4
Amplifier synchronization clock periods. The amplifiers can run with a clock frequency of up to
250 kHz (typical value).
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the
sampling point during at least 4 amplifier synchronization clock periods.
Amplified conversions can be synchronized to PSC events (See
Description in One Ramp Mode” on page 152
Centered Mode” on page
quency. In case the synchronization is done the ADC clock divided by 8, this synchronization
is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a
specific phase of CK
the first free running conversion) when CK
single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conver-
sion initiated by the user when CK
synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0
bits in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is
done on each synchronization event.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the
ADMUX must be configured as specified on
The ADC starting requirement is done by setting the ADSC bit of the ADCSRA Register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, two
timing diagram examples are shown
Bit
Read/Write
Initial Value
AMP1ND, AMP2PD:
ADC10..8, ACMP0, ACMP1, ACMP3, AMP0P, AMP0N, AMP1P, AMP1N, AMP2P Digital
Input Disable
7
0
-
-
ADC2
AMP2PD
. A conversion initiated by the user (i.e., all single conversions, and
152) or to the internal clock CK
6
0
-
ACMP0D
R/W
5
0
Figure 18-15
ADC2
AMP0PD
R/W
is high will take 14 ADC clock cycles due to the
ADC2
4
0
Table 18-5 on page
is low will take the same amount of time as a
and
AMP0ND
and
R/W
3
0
“Synchronization Source Description in
Figure
ADC
ACMP1D
ADC10D
R/W
equal to eighth the ADC clock fre-
2
0
18-16.
246.
AMP1PD
ACMP3D
ADC9D
“Synchronization Source
R/W
1
0
AMP1ND
ADC8D
R/W
0
0
7647G–AVR–09/11
DIDR1