ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 312

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

312
Atmel ATmega16/32/64/M1/C1
Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
Table 25-15. Parallel Programming Characteristics, V
Notes:
Symbol
V
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
XLOL
BVDV
OLDV
OHDZ
PP
XTAL1
DATA
BS1
XA0
XA1
OE
1. The timing requirements shown in
1. t
2. t
reading operation.
commands.
WLRH
WLRH_CE
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
XTAL1 Low to OE Low
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
Timing Requirements
ADDR0 (Low Byte)
LOAD ADDRESS
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
(LOW BYTE)
is valid for the Chip Erase command.
t
XLOL
t
OLDV
(1)
(1)
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 25-7
t
BVDV
(2)
(i.e., t
CC
= 5V ±10%
(HIGH BYTE)
DVXH
READ DATA
DATA (High Byte)
, t
11.5
Min
200
150
150
150
150
3.7
7.5
XHXL
67
67
67
67
67
67
67
0
0
0
0
0
t
OHDZ
, and t
Typ
XLDX
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
) also apply to
Max
12.5
250
250
250
250
4.5
7647G–AVR–09/11
1
9
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
A
s