ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 245

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

18.9
18.9.1
7647G–AVR–09/11
ADC Register Description
ADC Multiplexer Register – ADMUX
The ADC of the ATmega16/32/64/M1/C1 is controlled through 3 different registers. The ADC-
SRA and The ADCSRB registers which are the ADC Control and Status registers, and the
ADMUX which allows to select the Vref source and the channel to be converted.
The conversion result is stored on ADCH and ADCL register which contain respectively the
most significant bits and the less significant bits.
Bit
Read/Write
Initial Value
• Bit 7, 6 – REFS1, 0: ADC Vref Selection Bits
These 2 bits determine the voltage reference for the ADC.
The different setting are shown in
Table 18-4.
If bits REFS1 and REFS0 are changed during a conversion, the change will not take effect
until this conversion is complete (it means while the ADIF bit in ADCSRA register is set).
In case the internal Vref is selected, it is turned ON as soon as an analog feature needed it is
set.
• Bit 5 – ADLAR: ADC Left Adjust Result
Set this bit to left adjust the ADC result.
Clear it to right adjust the ADC result.
The ADLAR bit affects the configuration of the ADC result data registers. Changing this bit
affects the ADC data registers immediately regardless of any on going conversion. For a com-
plete description of this bit, see Section “ADC Result Data Registers – ADCH and ADCL”,
page 249.
AREFE
N
1
1
0
1
1
0
ISRCEN
0
0
0
0
0
x
ADC Voltage Reference Selection
REFS1
R/W
7
0
REFS1
0
0
0
1
1
1
REFS0
R/W
6
0
ADLAR
REFS0
0
1
1
0
1
1
R/W
Table
5
0
Atmel ATmega16/32/64/M1/C1
18-4.
MUX4
Description
External Vref on AREF pin, Internal Vref is switched off
AVcc with external capacitor connected on the AREF
pin
AVcc (no external capacitor connected on the AREF
pin)
Reserved
Internal 2.56V Reference voltage with external
capacitor connected on the AREF pin
Internal 2.56V Reference voltage
4
0
-
MUX3
R/W
3
0
MUX2
R/W
2
0
MUX1
R/W
1
0
MUX0
R/W
0
0
ADMUX
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