ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 119

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ATMEGA64M1-15MZ

Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA64M1-15MZ

Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
 Details
13.7.1
7647G–AVR–09/11
Compare Output Mode and Waveform Generation
Figure 13-5. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or
output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direc-
tion Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is
visible on the pin. The port override function is generally independent of the Waveform Gener-
ation mode, but there are some exceptions. Refer to
for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the
output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation.
The COMnx1:0 bits have no effect on the Input Capture unit.
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action
on the OCnx Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 13-2 on page
Table 13-3 on page
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOCnx strobe bits.
COMnx1
COMnx0
FOCnx
clk
I/O
See “16-bit Timer/Counter Register Description” on page 130.
130, and for phase correct and phase and frequency correct PWM refer to
131.
Waveform
Generator
Atmel ATmega16/32/64/M1/C1
Table 13-1 on page
D
D
D
PORT
DDR
OCnx
Q
Q
Q
Table
13-1,
130. For fast PWM mode refer to
1
0
Table 13-2
and
OCnx
Table 13-3
Pin
119

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