ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 222

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

17.5.15.2
17.5.16
222
Atmel ATmega16/32/64/M1/C1
OCD Support
UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will
be for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
This section describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O
view behavior in AVR Studio
Note:
1. LINCR:
2. LINSIR:
3. LINENR:
4. LINERR:
5. LINBTR:
6. LINBRRH & LINBRRL:
7. LINDLR:
8. LINIDR:
9. LINSEL:
10. LINDAT:
- LINCR[6..0] are R/W accessible,
- LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
- LIDST[2..0] and LBUSY are always Read accessible,
- LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly
by writing 1 or 0).
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR
bits.
- All bits are R/W accessible.
- All bits are R/W accessible,
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR.
- LBT[5..0] are R/W access only if LDISR is set,
- If LDISR is reset, LBT[5..0] are unchangeable.
- All bits are R/W accessible.
- All bits are R/W accessible.
- LID[5..0] are R/W accessible,
- LP[1..0] are Read accessible and are always updated on the fly.
- All bits are R/W accessible.
- All bits are in R/W accessible,
- Note that LAINC has no more effect on the auto-incrementation and the access to
the full FIFO is done setting LINDX[2..0] of LINSEL.
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted.
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7647G–AVR–09/11