ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 235

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

18.5
7647G–AVR–09/11
Changing Channel or Reference Selection
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 18-7. ADC Timing Diagram, Free Running Conversion
Table 18-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
Continuous updating resumes in the last eight ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA is set). Note that the conversion starts on the second following rising
CPU clock edge after ADSC is written. The user is thus advised not to write new channel or
reference selection values to ADMUX until two ADC clock cycle after ADSC is written.
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
ADC Conversion Time
Prescaler
Reset
MUX and REFS
Update
1
2
3
4
Atmel ATmega16/32/64/M1/C1
First Conversion
5
Sample &
Hold
6
13.5
25
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
7
One Conversion
8
Conversion
Complete
One Conversion
12
11
Conversion
Complete
Single Ended
Conversion,
13
12
Normal
15.5
13
3.5
14
14
Next Conversion
1
Sign and MSB of Result
LSB of Result
Sign and MSB of Result
2
MUX and REFS
Update
LSB of Result
Next Conversion
3
1
Prescaler
Reset
Auto Triggered
Sample & Hold
4
Conversion
2
5
16
2
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