ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 353

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

7647G–AVR–09/11
Note:
Figure 30-1. The Break Field
5. Wrong TSOFFSET manufacturing calibration value.
6. PD0-PD3 set to outputs and PD4 pulled down following power-on with external
7. LIN Break Delimitter
Erroneous value of TSOFFSET programmed in signature byte.
(TSOFFSET was introduced from REVB silicon).
Problem fix / workaround
To identify RevB with wrong TSOFFSET value, check device signature byte at
address 0X3F if value is not 0X42 (Ascii code ‘B’) then use the following formula.
TS_OFFSET(True) = (150*(1-TS_GAIN))+TS_OFFSET.
reset active.
At power-on with the external reset signal active the four I/O lines PD0-PD3 may be
forced into an output state. Normally these lines should be in an input state. PD4 may
be pulled down with internal 220 kOhm resistor. Following release of the reset line
(whatever is the startup time) with the clock running the I/Os PD0-PD4 will adopt their
intended input state.
Problem fix / workaround
None
In SLAVE MODE, a BREAK field detection error can occur under following condi-
tions. The problem occurs if 2 conditions occur simultaneously:
a. The DOMINANT part of the BREAK is (N+0.5)*Tbit long with N=13, 14,15, ...
b. The RECESSIVE part of the BREAK (BREAK DELIMITER) is equal to 1*Tbit.
The BREAK_high is not detected, and the 2nd bit of the SYNC field is interpreted as the
BREAK DELIMITER. The error is detected as a framing error on the first bits of the PID
or on subsequent Data or a Checksum error.
There is no error if BREAK_high is greater than 1*Tbit + 18%.
There is no problem in Master mode.
Workaround
None
LIN2.1 Protocol Specification paragraph 2.3.1.1 Break field says: “A break field is always gener-
ated by the master task(in the master node) and it shall be at least 13 nominal bit times of
dominant value, followed by a break delimiter, as shown in
shall be at least one nominal bit time long.”
(see note below)
Break
field
Header
Sync
field
Inter-byte space
Protected
identifier
field
Atmel ATmega16/32/64/M1/C1
Frame
Break
Data 1
Response space
Data 2
Response
Inter-byte space
Figure
Data N
30-1. The break delimiter
Checksum
delimiter
Break
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