ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 120

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

13.8
13.8.1
13.8.2
120
Modes of Operation
Atmel ATmega16/32/64/M1/C1
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare
Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For
non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or tog-
gle at a compare match
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer over-
flow interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value
can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the inter-
val between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero
when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn
(WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its res-
olution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs with either OCRnA or ICRn, and then counter
(TCNTn) is cleared.
(See “Compare Match Output Unit” on page
“Timer/Counter Timing Diagrams” on page
Figure
13-6. The counter value (TCNTn)
118.)
7647G–AVR–09/11
128.