ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 345

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

7647G–AVR–09/11
Mnemonics
MOVW
SWAP
PUSH
BSET
BCLR
BRID
ROR
MOV
SPM
OUT
POP
LSR
ROL
ASR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
SES
CLS
SEV
CLV
SET
SEH
CLH
LDD
LDD
LDS
STD
STD
STS
LPM
LPM
LPM
LSL
CLZ
CLT
SBI
CBI
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Operands
Rd, Z+q
Rd,Y+q
Rd, - X
Rd, - Y
Y+q,Rr
Rd, X+
Rd, Y+
Rd, Z+
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
Rd, -Z
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Z+, Rr
-Z, Rr
Rd, b
Rd, K
Rd, X
Rd, Y
Rd, Z
Rd, k
Rd, Z
Rd, P
Rr, b
X, Rr
Y, Rr
Z, Rr
P, Rr
k, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rr
s
s
k
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Branch if Interrupt Disabled
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Clear Bit in I/O Register
Global Interrupt Disable
Load Direct from SRAM
Global Interrupt Enable
Store Program Memory
Push Register on Stack
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Set Bit in I/O Register
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Logical Shift Right
Set Negative Flag
Logical Shift Left
Clear T in SREG
Load Immediate
Clear Zero Flag
Set T in SREG
Description
Swap Nibbles
Set Zero Flag
Load Indirect
Load Indirect
Load Indirect
Store Indirect
Store Indirect
Store Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Atmel ATmega16/32/64/M1/C1
Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0)
Rd(0) C,Rd(n+1) Rd(n),C Rd(7)
Rd(7) C,Rd(n) Rd(n+1),C Rd(0)
if ( I = 0) then PC
Rd(n+1)
Rd(n)
Rd(n)
Rd+1:Rd
Rd
Rd
X
Y
(X)
(Y)
Z
X
Y
(Z)
Rd
Z
Rd
SREG(s)
SREG(s)
Rd
Operation
Rd
Rd
STACK
I/O(P,b)
I/O(P,b)
(Y + q)
(Z)
(Z + q)
Rd(n+1), Rd(7)
X - 1, Rd
Y - 1, Rd
Z - 1, Rd
Rd(b)
X - 1, (X)
Y - 1, (Y)
Z - 1, (Z)
T
Rd
(X), X
Rd
(Y), Y
Rd
R0
Rd
Rd
Rd
(X)
(Y)
(Z)
Rd(n+1), n=0..6
Rr, X
Rr, Y
Rr, Z
(k)
Rd
Rd
(Z), Z
(Z), Z
P
Rd(n), Rd(0)
C
C
N
N
Z
Z
S
S
V
V
T
T
H
H
I
I
STACK
Rr(b)
(Y + q)
(Z + q)
R1:R0
1
0
Rr
1
0
1
0
1
0
1
0
(X)
(Y)
(Z)
(k)
Rr
(Z)
(Z)
1
0
1
0
1
0
Rr
Rr
Rr
Rr
Rr+1:Rr
K
P
T
Rr
Rr
Rr
X + 1
Y + 1
Z + 1
X + 1
PC + k + 1
Y + 1
1
0
Z+1
Z+1
1
0
(X)
(Y)
(Z)
Rr
Rr
Rr
0
0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
S
S
V
V
H
H
T
Z
Z
T
T
I
I
#Clocks
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
-
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