ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 220

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

17.5.11
17.5.12
17.5.13
220
Atmel ATmega16/32/64/M1/C1
Break-in-data
Checksum
Interrupts
CHECKSUM
=
255
According to the LIN protocol, the LIN/UART controller can detect the BREAK/SYNC field
sequence even if the break is partially superimposed with a byte of the response. When a
BREAK/SYNC field sequence happens, the transfer in progress is aborted and the processing
of the new frame starts.
On the slave node, the BREAK detection is processed with the synchronization setting avail-
able when the LIN/UART controller processed the (aborted) response. But the
re-synchronization restarts as usual. Due to a possible difference of timing reference between
the BREAK field and the rest of the frame, the time-out values can be slightly inaccurate.
The last field of a frame is the checksum.
In LIN 2.1, the checksum contains the inverted eight bit sum with carry over all data bytes and
the protected identifier. This calculation is called enhanced checksum.
In LIN 1.3, the checksum contains the inverted eight bit sum with carry over all data bytes.
This calculation is called classic checksum.
Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum
As shown in
are combined to drive two interrupts. Each of these flags have their respective enable interrupt
bit in LINENIR register.
(see
218).
–
• On slave node(s), an error is generated (i.e. LBERR in case of Tx Response or LFERR in
• On master node, the user (code) is responsible for this aborting of frame. To do this, the
case of Rx Response). Information on data error is also available, refer to the
17.5.7.5.
master task has first to abort the on-going communication (clearing LCMD bits - LIN Abort
command) and then to apply the Tx Header command. In this case, the abort error flag -
LABORT - is set.
unsigned char
Section 17.5.8 “xxOK Flags” on page 218
CHECKSUM
Figure 17-13 on page
n
0
DATA n
=
255
–
+
unsigned char
PROTECTED ID.
221, the four communication flags of the LINSIR register
n
0
DATA n
+
unsigned char
and
+
unsigned char
Section 17.5.9 “xxERR Flags” on page
n
0
DATA n
n
0
DATA n
+
PROTECTED ID.
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