ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 247

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

18.9.3
7647G–AVR–09/11
ADC Control and Status Register B– ADCSRB
• Bit 6– ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in
free running mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register.
See
• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with
the conversion result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock
of the ADC.
The different setting are shown in
Table 18-6.
Bit
Read/Write
Initial Value
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert
with an ADC clock frequency higher than 200KHz.
Clear this bit to reduce the power consumption of the ADC when the ADC clock frequency is
lower than 200KHz.
ADPS2
0
0
0
0
1
1
1
1
Table 18-7 on page
ADC Prescaler Selection
ADHSM
ADPS1
0
0
1
1
0
0
1
1
R/W
7
0
ISRCEN
248.
R/W
6
0
ADPS0
0
1
0
1
0
1
0
1
AREFEN
R/W
Table
5
0
Atmel ATmega16/32/64/M1/C1
18-6.
Division Factor
2
2
4
8
16
32
64
128
4
R
0
-
ADTS3
R/W
3
0
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ADTS0
R/W
0
0
ADCSRB
247