ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 194

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

16.10.10 CAN Bit Timing Register 3 - CANBT3
16.10.11 CAN Timer Control Register - CANTCON
194
Atmel ATmega16/32/64/M1/C1
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT3 is written.
• Bit 6:4 – PHS22:0: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by
the re-synchronization jump width. PHS2[2..0] shall be 1 and PHS1[2..0] (c.f.
“CAN Bit Timing” on page 170
• Bit 3:1 – PHS12:0: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ =
If BRP = 0, SMP must be cleared.
• Bit 7:0 – TPRSC7:0: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN
timer if the CAN controller is enabled.
T
clk
Initial Value
Initial Value
Read/Write
Read/Write
CANTIM
Bit
– 0 - the sampling will occur once at the user configured sampling point - SP.
– 1 - with three-point sampling configuration the first sampling will occur two
Bit
clocks before the user configured sampling point - SP, again at one
before SP and finally at SP. Then the bit level will be determined by a majority vote
of the three samples.
=
T
TPRSC7
clk
R/W
7
7
0
-
-
-
IO
x 8 x (CANTCON [7:0] + 1)
TPRSC6
PHS22
R/W
R/W
6
0
6
0
and
TPRSC5
PHS21
R/W
R/W
5
0
5
0
Section 16.4.3 “Baud Rate” on page
Tphs2 = Tscl x (PHS2 [2:0] + 1)
Tphs1 = Tscl x (PHS1 [2:0] + 1)
TPRSC4
PHS20
R/W
R/W
4
0
4
0
TPRSC3
PHS12
R/W
R/W
3
0
3
0
TPRSC2
PHS11
R/W
R/W
2
0
2
0
TRPSC1
PHS10
R/W
R/W
1
0
1
0
177).
T
clk
T
TPRSC0
clk
SMP
IO
R/W
R/W
0
0
0
0
Section 16.2.3
.
IO
7647G–AVR–09/11
clock
T
clk
CANTCON
CANBT3
IO