ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 142

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

14.6
142
Update of Values
Atmel ATmega16/32/64/M1/C1
POCRnRB
POCRnSB
POCRnSA
PSC Counter
Run
PSCOUTnA
PSCOUTnB
Note that in center aligned mode, POCRnRAH/L is not required (as it is in one-ramp mode) to
control PSC Output waveform timing. This allows POCRnRAH/L to be freely used to adjust
ADC synchronization (
Figure 14-7. Controlled Start and Stop Mechanism in Centered Mode
Note:
To avoid unasynchronous and incoherent values in a cycle, if an update of one of several val-
ues is necessary, all values are updated at the same time at the end of the cycle by the PSC.
The new set of values is calculated by sofware and the update is initiated by software.
Figure 14-8. Update at the end of complete PSC cycle.
The software can stop the cycle before the end to update the values and restart a new PSC
cycle.
Software
PSC
See “PSC Control Register – PCTL” on page
Regulation Loop
Calculation
Cycle
With Set i
Cycle
With Set i
See “Analog Synchronization” on page 149.
Cycle
With Set i
Writting in
PSC Registers
0
Cycle
With Set i
End of Cycle
Request for
an Update
154.(PCCYC = 1)
Cycle
With Set j
).
7647G–AVR–09/11