ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 152

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ATMEGA64M1-15MZ

Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA64M1-15MZ

Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
 Details
14.16.2
152
Atmel ATmega16/32/64/M1/C1
PSC Synchro Configuration – PSYNC
Bit
Read/Write
Initial Value
• Bit 7 – not use
not use
• Bit 6 – not use
not use
• Bit 5:4 – PSYNC21:0: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent from module 2
to the ADC for synchronization
• Bit 3:2 – PSYNC11:0: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent from module 1
to the ADC for synchronization
• Bit 1:0 – PSYNC01:0: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent from module 0
to the ADC for synchronization.
Table 14-8.
Table 14-9.
PSYNCn1
0
0
1
1
PSYNCn1
0
0
1
1
Synchronization Source Description in One Ramp Mode
Synchronization Source Description in Centered Mode
PSYNCn0
0
1
0
1
PSYNCn0
0
1
0
1
R/W
7
0
-
R/W
6
0
-
Description
Send signal on match with OCRnRA (during counting down of PSC).
The min value of OCRnRA must be 1.
Send signal on match with OCRnRA (during counting up of PSC). The
min value of OCRnRA must be 1.
no synchronization signal
no synchronization signal
Description
Send signal on leading edge of PSCOUTnA(match with OCRnSA)
Send signal on trailing edge of PSCOUTnA(match with OCRnRA or
fault/retrigger on part A)
Send signal on leading edge of PSCOUTnB (match with OCRnSB)
Send signal on trailing edge of PSCOUTnB (match with OCRnRB or
fault/retrigger on part B)
PSYNC21
R/W
5
0
PSYNC20
R/W
4
0
PSYNC11
R/W
3
0
PSYNC10
R/W
2
0
PSYNC01
R/W
1
0
PSYNC00
R/W
0
0
7647G–AVR–09/11
PSYNC

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