ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 234

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

234
Atmel ATmega16/32/64/M1/C1
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See
ence Selection” on page 235
A normal conversion takes 15.5 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the ana-
log circuitry.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal con-
version and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver-
sion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a
new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the sam-
ple-and-hold takes place two ADC clock cycles after the rising edge on the trigger source
signal. Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion
completes, while ADSC remains high. For a summary of conversion times, see
Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 18-5. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADIF
ADCH
ADCL
ADSC
1
2
1
MUX and REFS
Update
2
MUX and REFS
Update
for details on differential conversion timing.
12
3
4
13
5
14
6
Sample & Hold
15
7
Sample & Hold
16
8
First Conversion
One Conversion
22
10
23
11
Conversion
Complete
24
“Changing Channel or Refer-
12
25
Conversion
Complete
13
26
14
27
Sign and MSB of Result
LSB of Result
28
Next Conversion
1
Table
Sign and MSB of Result
2
7647G–AVR–09/11
MUX and REFS
Update
Next
Conversion
3
1
LSB of Result
18-1.
2
and REFS
Update
MUX
3