ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 22

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

4.3
4.3.1
22
EEPROM Data Memory
Atmel ATmega16/32/64/M1/C1
EEPROM Read/Write Access
Figure 4-3.
The ATmega16/32/64/M1/C1 contains 512/1024/2048 bytes of data EEPROM memory. It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-
ters, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
Downloading” on page 313
mands” on page 301
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains
instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency
used.
in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction
is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the
next instruction is executed.
See “Preventing EEPROM Corruption” on page
CC
is likely to rise or fall slowly on power-up/down. This causes the device for some
Address
On-chip Data SRAM Access Cycles
clk
Data
Data
WR
CPU
RD
respectively.
, and
Compute Address
“Parallel Programming Parameters, Pin Mapping, and Com-
T1
Memory Access Instruction
Address valid
Table
T2
27.for details on how to avoid problems
4-2. A self-timing function, however,
Next Instruction
T3
7647G–AVR–09/11
“Serial