ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 164
ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
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15.2.4
164
Atmel ATmega16/32/64/M1/C1
SPI Control Register – SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the
if the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable
SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is
low when idle. Refer to
summarized below:
Table 15-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first)
or trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 15-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
Bit
Read/Write
Initial Value
CPOL
CPHA
0
1
0
1
CPOL Functionality
CPHA Functionality
SPIE
R/W
7
0
Figure 15-3
SPE
R/W
6
0
DORD
R/W
5
0
and
Figure 15-3
Leading Edge
Leading Edge
Figure 15-4
Sample
MSTR
Falling
Rising
R/W
Setup
4
0
and
CPOL
R/W
for an example. The CPOL functionality is
3
0
Figure 15-4
CPHA
R/W
2
0
for an example. The CPOL
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
0
0
7647G–AVR–09/11
SPCR
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