ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 252

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

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Atmel ATmega16/32/64/M1/C1
Figure 18-16. Amplifier synchronization timing diagram
In order to have a better understanding of the functioning of the amplifier synchronization, a
timing diagram example is shown
It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-
sion is started at the next amplifier clock event following the last auto trigger event selected
thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running
mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
Block
ADC
PSC
(Sync Clock)
Si g nal to be
PS Cn_ASY
AMPLI_clk
measu red
CK ADC
Activity
ADSC
ADC
ADSC is set when the amplifier output is changing due to the amplifier clock
switch
Figure
Sampling
ADC
Conv
ADC
18-15.
ADC Result
Ready
Sampling
Aborted
ADC
Sampling
7647G–AVR–09/11
ADC
Valid sample
Conv
ADC
ADC Result
Ready