ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 172

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

16.2.3.7
16.2.3.8
16.2.3.9
16.2.3.10
16.2.3.11
16.2.3.12
16.2.4
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Atmel ATmega16/32/64/M1/C1
Arbitration
Information Processing Time
Bit Lengthening
Bit Shortening
Synchronization Jump Width
Programming the Sample Point
Synchronization
It is the time required for the logic to determine the bit level of a sampled bit.
The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN.
Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time,
PS2 minimum shall not be less than the IPT.
As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2
may be shortened to compensate for oscillator tolerances. If, for example, the transmitter
oscillator is slower than the receiver oscillator, the next falling edge used for resynchronization
may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and
the end of the bit time.
If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling
edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened
in order to adjust the sample point for bit N+1 and the end of the bit time
The limit to the amount of lengthening or shortening of the Phase Segments is set by the
Resynchronization Jump Width.
This segment may not be longer than Phase Segment 2.
Programming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization
Jump Width can be programmed to its maximum. This maximum capacity to shorten or
lengthen the bit time decreases the sensitivity to node oscillator tolerances, so that lower cost
oscillators such as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows a
poorer bus topology and maximum bus length.
Hard synchronization occurs on the recessive-to-dominant transition of the start bit. The bit
time is restarted from that edge.
Re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the Syn-
chronization Segment in a message.
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multi-
ple Access with Arbitration on Message Priority”.
During transmission, arbitration on the CAN bus can be lost to a competing device with a
higher priority CAN Identifier. This arbitration concept avoids collisions of messages whose
transmission was started by more than one node simultaneously and makes sure the most
important message is sent first without time loss.
7647G–AVR–09/11