ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 192

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

16.10.6
16.10.7
16.10.8
192
Atmel ATmega16/32/64/M1/C1
CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1
CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1
CAN Bit Timing Register 1 - CANBT1
• Bits 5:0 - IEMOB5:0: Interrupt Enable by MOb
Note:
• Bit 15:6 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, it must be written
to zero when CANIE1 & CANIE2 are written.
• Bits 5:0 - SIT5:0: Status of Interrupt by MOb
Note:
• Bit 15:6 – Reserved Bits
These bits are reserved for future use.
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT1 is written.
Initial Value
Initial Value
Initial Value
Initial Value
Initial Value
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Bit
Bit
– 0 - interrupt disabled.
– 1 - MOb interrupt enabled
Bit
Bit
– 0 - no interrupt.
– 1- MOb interrupt.
Bit
Example: CANIE2 = 0000 1100
Example: CANSIT2 = 0010 0001
R/W
15
15
R
R
R
7
0
0
7
0
0
7
-
-
-
-
-
-
-
BRP5
R/W
R/W
R/W
14
14
R
R
6
0
0
6
0
0
6
0
-
-
-
-
IEMOB5
BRP4
SIT5
R/W
R/W
R/W
13
13
R
R
5
0
0
5
0
0
5
0
-
-
b
b
: enable of interrupts on MOb 2 & 3.
: MOb 0 & 5 interrupts.
IEMOB4
BRP3
SIT4
R/W
R/W
R/W
12
12
R
R
4
0
0
4
0
0
4
0
-
-
IEMOB3
BRP2
SIT3
R/W
R/W
R/W
11
11
R
R
3
0
0
3
0
0
3
0
-
-
IEMOB2
BRP1
SIT2
R/W
R/W
R/W
10
10
R
R
2
0
0
2
0
0
2
0
-
-
IEMOB1
BRP0
SIT1
R/W
R/W
R/W
R
R
1
9
0
0
1
9
0
0
1
0
-
-
IEMOB0
SIT0
R/W
R/W
R
R
0
8
0
0
0
8
0
0
0
-
-
-
-
-
7647G–AVR–09/11
CANSIT2
CANSIT1
CANBT1
CANIE2
CANIE1