ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 236

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ATMEGA64M1-15MZ

Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA64M1-15MZ

Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
 Details
18.5.1
18.5.2
236
Atmel ATmega16/32/64/M1/C1
ADC Input Channels
ADC Voltage Reference
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
Note:
The reference voltage for the ADC (V
ended channels that exceed V
either AV
AV
erated from the internal bandgap reference (V
the external AREF pin is directly connected to the ADC, and the reference voltage can be
made more immune to noise by connecting a capacitor between the AREF pin and ground.
V
a high impedant source, and only a capacitive load should be connected in a system.
REF
1. When ADATE or ADEN is cleared.
2. During conversion, with taking care of the trigger source event, when it is possible.
3. After a conversion, before the interrupt flag used as trigger source is cleared.
• In Single Conversion mode, always select the channel before starting the conversion. The
• In Free Running mode, always select the channel before starting the first conversion. The
• In Free Running mode, because the amplifier clear the ADSC bit at the end of an amplified
CC
channel selection may be changed one ADC clock cycle after writing one to ADSC.
However, the simplest method is to wait for the conversion to complete before changing the
channel selection.
channel selection may be changed one ADC clock cycle after writing one to ADSC.
However, the simplest method is to wait for the first conversion to complete, and then
change the channel selection. Since the next conversion has already started automatically,
the next result will reflect the previous channel selection. Subsequent conversions will
reflect the new channel selection.
conversion, it is not possible to use the free running mode, unless ADSC bit is set again by
soft at the end of each conversion.
can also be measured at the AREF pin with a high impedant voltmeter. Note that V
is connected to the ADC through a passive switch. The internal 2.56V reference is gen-
When The ADC and COMPARATOR share the same channel (Possible configuration for
AMP1+, AMP1- and AMP2-), up to revision B of ATmega32M1 the comparator is disconnected
during the sampling of the ADC. For ATmega16/64 and ATmega32 revision C, the COMPARA-
TOR is always connected.
CC
, internal 2.56V reference, or external AREF pin.
REF
will result in codes close to 0x3FF. V
REF
) indicates the conversion range for the ADC. Single
BG
) through an internal amplifier. In either case,
REF
can be selected as
7647G–AVR–09/11
REF
is

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